182.701 HW/SW Codesign
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2023W, LU, 4.5h, 4.5EC


  • Semester hours: 4.5
  • Credits: 4.5
  • Type: LU Laboratory Exercise
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to

  •  perform an efficient HW/SW partitioning for a given problem
  •  understand the implications of a decision for a HW- or a SW-implementation
  • develop and integrate custom hardware components for a soft-core processor
  •  complete autonomously a small challenging problem in a team
  •  accomplish time management for a small project

Subject of course

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code in assembly when compilers do not achieve the optimum
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

Teaching methods

The students learn to handle the soft-core processor Nios II from Intel and the corresponding tools such as the Platform Designer and Quartus. There is furthermore a major focus on giving the students a lot of room to make their own decisions.

Mode of examination


Additional information

An overview and introduction to this course (as well as other Master courses offered by the ECS group) will be given on

Oct 3rd 2023 at 9:15 in the seminar room DE0110 (Treitlstrasse 3, 1st floor)


ECTS Breakdown

98.5 h    Solving the task assignments
      4 h    Preparation of the mid-term presentation
      4 h    Preparation of the final presentation
      6 h    Presence at the presentations/exercise interviews
112.5 h ( = 4.5 ECTS)



Course dates

Tue09:00 - 11:0003.10.2023Seminarraum DE0110 Course Introduction (+ preview/intro of other master courses of the institute)
Fri11:00 - 12:0013.10.2023Seminarraum DE0110 Get-to-Know Q&A
Fri11:00 - 12:0020.10.2023Seminarraum DE0110 Get-to-Know Q&A
Fri10:00 - 11:0027.10.2023 Zoom: https://tuwien.zoom.us/j/95270238437Get-to-Know Q&A
Tue09:00 - 11:0007.11.2023Seminarraum DE0110 Main Task Presentation and Q&A
Tue09:00 - 13:0005.12.2023Seminarraum DE0110 Midterm Presentations
Tue09:00 - 13:0023.01.2024Seminarraum DE0110 Final Presentations

Examination modalities

demonstration of the acchieved solution to the supervisor and defence of implemenation details
presentation of a proper concept to the remaining groups and discussion of chosen design decisions.

The FPGA development boards and the design software are provided in the TILab. Additionally remote access to the required hardware  is possible.
For the group-phase one FPGA board per group can be borrowed.


Course registration

Begin End Deregistration end
18.09.2023 14:00 06.10.2023 23:59 06.10.2023 23:59


Study CodeObligationSemesterPrecon.Info
066 504 Master programme Embedded Systems Not specified
066 938 Computer Engineering Mandatory elective


No lecture notes are available.

Previous knowledge

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization

Preceding courses

Accompanying courses

Continuative courses



if required in English