182.701 HW/SW Codesign
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2021W, LU, 4.5h, 4.5EC
Quinn ECTS survey


  • Semester hours: 4.5
  • Credits: 4.5
  • Type: LU Laboratory Exercise
  • Format: Online

Learning outcomes

After successful completion of the course, students are able to

  •  perform an efficient HW/SW partitioning for a given problem
  •  understand the implications of a decision for a HW- or a SW-implementation
  • develop and integrate custom hardware components for a soft-core processor
  •  complete autonomously a small challenging problem in a team
  •  accomplish time management for a small project

Subject of course

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code in assembly when compilers do not achieve the optimum
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

Teaching methods

The students learn to handle the soft-core processor Nios II from Intel and the corresponding tools such as the Platform Designer and Quartus. There is furthermore a major focus on giving the students a lot of room to make their own decisions.

Mode of examination


Additional information

An overview and introduction to this course (as well as other Master courses offered by the ECS group) will be given on

Oct 5th 2021 at 9am at   https://tuwien.zoom.us/j/96478348061


ECTS Breakdown

98.5 h    Solving the task assignments
      4 h    Preparation of the mid-term presentation
      4 h    Preparation of the final presentation
      6 h    Presence at the presentations/exercise interviews
112.5 h ( = 4.5 ECTS)



Course dates

Tue09:00 - 10:0005.10.2021 https://tuwien.zoom.us/j/96478348061Course Introduction (+ preview/intro of other master courses of the institute)
Fri10:00 - 11:3008.10.2021 https://tuwien.zoom.us/j/95270238437Tool (Quartus, Nios 2, Platform Deseigner, Remote Access) and Get-to-Know Task Q&A
Wed14:00 - 16:0003.11.2021FAV Hörsaal 1 - INF Hardware modelling lecture and maintask Q/A
Wed14:00 - 18:0001.12.2021FAV Hörsaal 1 - INF Midterm Presentations
Wed14:00 - 16:0026.01.2022FAV Hörsaal 1 - INF Final Presentation

Examination modalities

demonstration of the acchieved solution to the supervisor and defence of implemenation details
presentation of a proper concept to the remaining groups and discussion of chosen design decisions.

Distance-Learning Information:

This course will be held primarily online. Lectures and meetings will, however, if possible hel in presence at the university. Exercise interviews are again held online (a webcam is required for identity verification).

For the initial phase of the course (non-group phase) a remote access to the required hardware (FPGA development board ) is provided. For the group-phase one FPGA board per group can be borrowed. Physical access to the computer lab (TILab) is not possible during this semester!


Course registration

Begin End Deregistration end
13.09.2021 14:00 15.10.2021 23:59 15.10.2021 23:59


Study CodeObligationSemesterPrecon.Info
066 504 Master programme Embedded Systems Not specified
066 938 Computer Engineering Mandatory elective


No lecture notes are available.

Previous knowledge

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization

Preceding courses

Accompanying courses

Continuative courses



if required in English