After successful completion of the course, students are able to

• name the basic properties of hardware designs
• apply basic VHDL commands and concepts
• develop purely combinatorial logic, synchronous logic and logic with an internal state
• formulate suitable solutions in VHDL to solve a given problem
• develop a systematic plan for implementation and verification of a hardware design
• identify design challenges and provide appropriate solutions

Hardware Development

• motivation and introduction
• key properties and differences to software design
• challenges and hardware description languages

VHDL

• entity, architecture and configuration
• structural and behavioral programming
• testbenches, components and packages
• process, sensitivity list and control flow commands
• state machines, three process method
• data types, attributes, libraries, subprograms, ....

Hardware Modeling

• design flow including verification
• systematic and hierarchical designs, implementation and verification
• circuit design challenges
• state machine design
• efficient and sustainable hardware description
• synthesis and optimizations
• functional/formal verification, automated testing

Tools

• Quartus (synthesis)
• Questasim (verification)

Flipped Classroom Concept

• content is presented in short videos, which can be consumed completely autonomously in the TUWEL course
• short quizes and voluntary training examples support the learning process by giving immediate feedback
• anonymous feedback and question to every video available
• forum for exchange among students and for communication with the teaching staff
• twice a week Zoom meeting for discussion of remaining questions

Start of the lecture from February 26th anytime individually possible! Visit the TUWEL course and get going!

• heavily blocked at begin of semester to assure quick introduction to VHDL (required especially for LU Digital Design and Computer Architecture)
• tools for simulation and synthesis are presented in the lecture

ECTS Breakdown

25 h    Videos and Quizes
12.5 h Continuous engagement with the lecture contents, preparation time for final exam
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37.5h  (= 1.5 ECTS)

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Please note that this is not a typical lecture (see Methods section). The listed events are question and answer sessions, where you have the possibility to ask questions regarding the course materials and we can discuss problems with the self-assesment tests in TUWEL. Participation is voluntary.

!!! The course starts with an introductory event on March 7 2024, 9:00 am in the lecture room FAV Hörsaal 1 - INF. It is a joint event covering the courses “Digital Design and Computer Architecture” (LU, 182.695) and “Hardware Modeling” (VO, 182.696) !!!

Please note that “Computer Organization and Design” (VO, 182.690) is not held in the sommer term 2024.

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Closed book exam on paper in presence (60 min).

• logic gates (OR, MUX, FF, etc.)
• Mealy / Moore automata
• Y-diagram
• control flow concepts (if-then-else, loops, etc.)
• synchronous circuit design
• hardware design flow including verification