182.696 Hardware Modeling
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2023S, VO, 1.5h, 1.5EC, to be held in blocked form
TUWEL

Properties

  • Semester hours: 1.5
  • Credits: 1.5
  • Type: VO Lecture
  • Format: Online

Learning outcomes

After successful completion of the course, students are able to

  • name the basic properties of hardware designs
  • apply basic VHDL commands and concepts
  • develop purely combinatorial logic, synchronous logic and logic with an internal state
  • formulate suitable solutions in VHDL to solve a given problem
  • develop a systematic plan for implementation and verification of a hardware design
  • identify design challenges and provide appropriate solutions

Subject of course

Hardware Development

  • motivation and introduction
  • key properties and differences to software design
  • challenges and hardware description languages

VHDL

  • entity, architecture and configuration
  • structural and behavioral programming
  • testbenches, components and packages
  • process, sensitivity list and control flow commands
  • state machines, three process method
  • data types, attributes, libraries, subprograms, ....

Hardware Modeling

  • design flow including verification
  • systematic and hierarchical designs, implementation and verification
  • circuit design challenges
  • state machine design
  • efficient and sustainable hardware description
  • synthesis and optimizations
  • functional/formal verification, automated testing

Tools

  • Quartus (synthesis)
  • Questasim (verification)

Teaching methods

Flipped Classroom Concept

  • content is presented in short videos, which can be consumed completely autonomously in the TUWEL course
  • short quizes and voluntary training examples support the learning process by giving immediate feedback
  • anonymous feedback and question to every video available
  • forum for exchange among students and for communication with the teaching staff
  • twice a week Zoom meeting for discussion of remaining questions

Mode of examination

Written

Additional information

Start of the lecture from February 27th anytime individually possible! Visit the TUWEL course and get going!

  • heavily blocked at begin of semester to assure quick introduction to VHDL (required especially for LU Digital Design and Computer Architecture)
  • tools for simulation and synthesis are presented in the lecture

ECTS Breakdown

25 h    Videos and Quizes
12.5 h Continuous engagement with the lecture contents, preparation time for final exam
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37.5h  (= 1.5 ECTS)

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The actual events are always Monday 16:00 (Zoom) and Thursday 09:00 (FAV Hörsaal 1).

!!! The course starts with an introductory event on 03.Mar.2022, 9:00 am. It is a joint event covering the courses “Digital Design and Computer Architecture” (LU, 182.695), “Hardware Modeling” (VO, 182.696) and “Computer Organization and Design” (VO, 182.690). !!!

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Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Thu09:00 - 11:0002.03.2023 - 22.06.2023FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu09:00 - 11:0002.03.2023 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Course Introduction (HWmod, DDCA, CA)
Mon16:00 - 17:0006.03.2023 - 27.03.2023 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Hardware Modeling - Single appointments
DayDateTimeLocationDescription
Thu02.03.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu02.03.202309:00 - 11:00 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Course Introduction (HWmod, DDCA, CA)
Mon06.03.202316:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu09.03.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Mon13.03.202316:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu16.03.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Mon20.03.202316:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu23.03.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Mon27.03.202316:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu30.03.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu20.04.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu27.04.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu04.05.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu11.05.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu25.05.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu01.06.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu15.06.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Thu22.06.202309:00 - 11:00FAV Hörsaal 1 Helmut Veith - INF Lecture
Course is held blocked

Examination modalities

Closed book exam on paper in presence (60 min).

Exams

DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Tue11:00 - 13:0002.07.2024Informatikhörsaal - ARCH-INF written02.05.2024 00:00 - 30.06.2024 23:59TISSEnd of study year exam

Course registration

Begin End Deregistration end
20.02.2023 00:00 02.04.2023 23:59

Curricula

Study CodeObligationSemesterPrecon.Info
033 535 Computer Engineering Mandatory4. SemesterSTEOP
Course requires the completion of the introductory and orientation phase

Literature

No lecture notes are available.

Previous knowledge

  • logic gates (OR, MUX, FF, etc.)
  • Mealy / Moore automata
  • Y-diagram
  • control flow concepts (if-then-else, loops, etc.)
  • synchronous circuit design
  • hardware design flow including verification

Preceding courses

Accompanying courses

Continuative courses

Miscellaneous

Language

English