182.696 Hardware Modeling
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2019S, VO, 1.5h, 1.5EC, to be held in blocked form
TUWEL

Properties

  • Semester hours: 1.5
  • Credits: 1.5
  • Type: VO Lecture

Aim of course

Students finishing this course are able to

  • name the main differences between hardware and software designs
  • use basic VHDL commands and concepts
  • demonstrate the behavior of hardware modules described in VHDL
  • develop hardware designs with an internal state based on textual specifications
  • implement small hardware designs using the hardware description language VHDL
  • describe the development process of  a proper implementation strategy
  • discuss solutions for problems that appear in real world implementations
  • describe the tool design flow and useful mechanisms to control it
  • explain the single steps of the verification of a hardware implementation

Subject of course

Hardware Development

  • motivation and introduction
  • key properties and differences to software design
  • challenges and hardware description languages

VHDL

  • entity, architecture and configuration
  • structural and behavioral programming
  • testbenches, components and packages
  • process, sensitivity list and control flow commands
  • state machines, three process method
  • data types, attributes, libraries, subprograms, ....

Hardware Modeling

  • design flow including verification
  • specification, partitioning and design descriptions
  • handling real life problems
  • state machine design
  • programming towards code reusability
  • synthesis and optimizations
  • functional/formal verification, automated testing

Tools

  • Quartus (synthesis)
  • Modelsim (verification)

Additional information

  • recordings (slides+audio) will be available in TUWEL after the lecture
  • used tools are presented in the lecture

ECTS Breakdown

16 h    Lecture time
21.5 h Continuous engagement with the lecture contents, preparation time for final exam
------------------------------------------------------------------------------------------------------------------------
37.5h  (= 1.5 ECTS)

WARNING: There will be no lecture on 20.3. and 3.4. !

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Wed09:00 - 11:0006.03.2019 - 27.03.2019HS 17 Friedrich Hartmann - ARCH HW Modeling VO
Fri13:00 - 15:0008.03.2019 - 05.04.2019EI 8 Pötzl HS - QUER HW Modeling VO
Hardware Modeling - Single appointments
DayDateTimeLocationDescription
Wed06.03.201909:00 - 11:00HS 17 Friedrich Hartmann - ARCH HW Modeling VO
Fri08.03.201913:00 - 15:00EI 8 Pötzl HS - QUER HW Modeling VO
Wed13.03.201909:00 - 11:00HS 17 Friedrich Hartmann - ARCH HW Modeling VO
Fri15.03.201913:00 - 15:00EI 8 Pötzl HS - QUER HW Modeling VO
Fri22.03.201913:00 - 15:00EI 8 Pötzl HS - QUER HW Modeling VO
Wed27.03.201909:00 - 11:00HS 17 Friedrich Hartmann - ARCH HW Modeling VO
Fri29.03.201913:00 - 15:00EI 8 Pötzl HS - QUER HW Modeling VO
Fri05.04.201913:00 - 15:00EI 8 Pötzl HS - QUER HW Modeling VO
Course is held blocked

Examination modalities

written exam on paper, cheat sheet (see TUWEL) provided

Exams

DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Tue11:00 - 13:0002.07.2024Informatikhörsaal - ARCH-INF written02.05.2024 00:00 - 30.06.2024 23:59TISSEnd of study year exam

Course registration

Begin End Deregistration end
18.02.2019 00:00 31.03.2019 23:59

Curricula

Study CodeObligationSemesterPrecon.Info
033 535 Computer Engineering Mandatory4. SemesterSTEOP
Course requires the completion of the introductory and orientation phase

Literature

slides, audio recordings, literature links and examples for training are available in TUWEL

Previous knowledge

  • logic gates (OR, MUX, FF, etc.)
  • Mealy / Moore automata
  • Y-diagram
  • control flow concepts (if-then-else, loops, etc.)
  • synchronous circuit design
  • hardware design flow including verification

Preceding courses

Accompanying courses

Continuative courses

Miscellaneous

Language

English