Students finishing this course are able to

• describe the differences between hardware and software development
• name and explain basic VHDL commands and concepts (concurrent, structural, sequential, ...)
• analyse and edit existing hardware descriptions written in VHDL
• implement a simple hardware design using a high level language (VHDL)
• (automatically) simulate and verify given hardware designs
• develop a reasonable hardware design based on a specification

• properties of modeling hardware
• hardware vs. software development
• VHDL
• structural vs. concurrent vs. sequential programming
• state machines
• test benches
• tool support
• Quartus (syntheses)
• Modelsim (simulation)
• reasonable implementation of a specification
• suitable partitioning
• guidelines for coding and synthesis
• (automatic) verification

• recordings (slides+audio) will be available in TUWEL after the lecture
• used tools are presented in the lecture

ECTS Breakdown

16 h    Lecture time
21.5 h Continuous engagement with the lecture contents, preparation time for final exam
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37.5h  (= 1.5 ECTS)

WARNING: Lecture dates and times changed!

There will be no lecture on 21.3., 23.3. and 18.4. !

written exam

• logic gates (OR, MUX, FF, etc.)
• Mealy / Moore automata
• Y-diagram
• control flow concepts (if-then-else, loops, etc.)
• synchronous circuit design
• hardware design flow including verification