182.695 Digital Design and Computer Architecture
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2023S, LU, 7.5h, 7.5EC


  • Semester hours: 7.5
  • Credits: 7.5
  • Type: LU Laboratory Exercise
  • LectureTube course
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to

  • develop combinatorial logic
  • implement simple state machines
  • introduce a pipelining concept in CPUs
  • carry out a synthesis and simulation of VHDL code in appropriate software tools
  • program an FPGA with the generated hardware
  • verify the hardware systematically using simulations, tests on the FPGA and measurements

Subject of course

Hands on application of the contents of the lectures "Digital Design", "Hardware Modeling" and "Computer Organization and Design"

  • design flow (synthesis & simulation)
  • testing & debugging of a VHDL design
  • handling digital measurement instruments
  • modern processor architecture

Teaching methods

  • Different tasks have to be solved autonomously/in groups
  • The used FPGA boards (Altera chips) are programmed using the synthesis software Quartus. For simulating the digital circuit the simulation tool Questa/Modelsim will be used (free for download on the web).
  • We provide a VM with all the required tools preinstalled.
  • The FPGA boards are programmed either directly in the TILab or using remote access to the TILab. A debug interface and a camera setup are used to observe the output of the FPGA boards.
  • Tutors will be available in the lab or over TU Chat and Zoom.
  • Both the midterm and the final exam will take place in the lab


Mode of examination


Additional information

!!! The course starts with an introductory event on 02.Mar.2023, 9:00 am in the lecture room FAV Hörsaal 1 - INF. It is a joint event covering the courses “Digital Design and Computer Architecture” (LU, 182.695), “Hardware Modeling” (VO, 182.696) and “Computer Organization and Design” (VO, 182.690). !!!

ECTS Breakdown

4.5 h   Introduction lectures 
 92 h   Tasks first part (Digital design basics)
  8 h   Preparation for midterm exam
 75 h   Tasks second part (Computer architecture)
  8 h   Preparation for final exam
187.5 h (= 7.5 ECTS)




Course dates

Thu09:00 - 11:0002.03.2023FAV Hörsaal 1 Helmut Veith - INF Introductory Event
Mon13:00 - 15:0006.03.2023 CANCELEDLecture: Digital Design Basics and Repetition (CANCELED)
Thu09:00 - 11:0009.03.2023FAV Hörsaal 1 Helmut Veith - INF Lecture: Digital Design Basics and Repetition
Mon10:00 - 12:0013.03.2023HS 17 Friedrich Hartmann - ARCH Lecture: FPGA Design Flow
Fri07:30 - 20:0005.05.2023InfLab Frogger Midterm Exam
Fri07:30 - 20:0005.05.2023InfLab Pong Midterm Exam
Fri07:30 - 20:0005.05.2023InfLab Q*bert Midterm Exam
Mon07:30 - 20:0003.07.2023InfLab Pong Final Exam
Mon07:30 - 20:0003.07.2023InfLab Frogger Final Exam
Mon07:30 - 20:0003.07.2023InfLab Q*bert Final Exam

Examination modalities

The final grade results from

  • the quality of the provided solutions to the assignments (50%)
  • performance in the two written exams in the middle and at the end of the semester (50%)

Course registration

Begin End Deregistration end
16.02.2023 12:00 05.03.2023 23:59 05.03.2023 23:59


Study CodeObligationSemesterPrecon.Info
033 535 Computer Engineering Mandatory4. SemesterSTEOP
Course requires the completion of the introductory and orientation phase


No lecture notes are available.

Previous knowledge

  • This course assumes that Hardware Modeling is done in parallel.
  • Basic programming knowledge (especially C)
  • Digital Design Basics
    • Combinational Logic: basic gates (AND, OR, XOR, etc.)
    • Sequential components (Flip-Flops, Latches)
    • Basic Boolean circuits
    • Memory (RAM/FIFO)
    • CMOS Basics (Driver, tri-state, pullup/pulldown resisitors, etc.)
    • Synchronizer
  • State Machines
    • Register. next-state/output logic
    • Moore vs. Mealy

Preceding courses

Accompanying courses

Continuative courses