After successful completion of the course, students are able to (utlitizing the hardware description language VHDL)

• develop combinatorial logic
• implement simple state machines
• introduce a piplining concept in CPUs
• carry out a synthesis in an appropiate software tool
• program an FPGA with the generated hardware
• verify the hardware systematically using simulations, tests on the FPGA and measurements on a logic analyzer

Hands on application of the contents of the lectures "Digital Design", "Hardware Modeling" and "Computer Organzation and Design"

• design flow (synthesis & simulation)
• testing & debugging of a VHDL design
• handling digital measurement instruments
• modern processor architecture

• different tasks have to be solved autonomously/in groups
• the used FPGA boards (Altera chips) are programmed using the synthesis software Quartus and verified using the simulation tool Questa (free for download on the web)
• lab places in the TILab are available: The lab also features logic analyzers for measurements and tutors for common questions

ECTS Breakdown

 75 h      Tasks first part (Digital design basics)
 15 h      Preperation for midterm exam
 75 h      Tasks second part (Computer architecture)
 22.5 h   Preperation for final exam
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187.5 h (= 7.5 ECTS)

The final grade results from

• the quality of the provided solutions to the assignments
• performance in the two written exams in the middle and at the end of the semester