Time-predictable Multi-Core Architecture for Embedded Systems

01.09.2011 - 31.08.2014
Standard computer architecture is driven by the following paradigm: Make the common case fast and the uncommon case correct. This design approach leads to architectures where the average-case execution time is optimized at the expense of the worst-case execution time (WCET). Modeling the dynamic features of current processors, memories, and interconnects for WCET analysis often results in computationally infeasible problems. The bounds calculated by the analysis are thus overly conservative. We need a sea change and we shall take the constructive approach by designing computer architectures where predictable timing is a first-order design factor. For real-time systems we propose to design architectures with a new paradigm: Make the worst case fast and the whole system easy to analyze. Despite the advantages of a analyzable system resources, only a few research projects exist in the field of hardware optimized for the WCET. Within the project we will propose novel solutions for time-predictable multi-core and many-core system architectures. The resulting time-predictable resources (processor, interconnect, memories, etc.) will be a good target for WCET analysis and the WCET performance will be outstanding compared to current processors. Time-predictable caching and time-predictable chip-multiprocessing (CMP) will provide a solution for the need of more processing power in the real-time domain. Next to the hardware (processor, interconnect, memories), a compiler infrastructure will be developed in the project. WCET aware optimization methods will be developed along with detailed timing models such that the compiler benefits from the known behavior of the hardware. The WCET analysis tool aiT will be adapted to support the developed hardware and guide the compilation.








  • European Commission (EU) RP7 I.3 ZUSAMMENARBEIT Informations- und Kommunikationstechnologien 7.Rahmenprogramm für Forschung Europäische Kommission - Rahmenprogamme Europäische Kommission Ausschreibungskennung FP7-ICT-2011-7 Antragsnummer 288008


  • Information and Communication Technology


embedded systemsembedded systems
real-time systemsreal-time systems
chip multiprocessingchip multiprocessing
VLIW processorVLIW processor

Externe Partner_innen

  • Institut für Computersprachen