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Exploiting Synchrony for Transparent Communication Services Testing
01.10.2005 - 30.09.2008
Research funding project
Electronics is already being widely used in cars (e.g. infotainment and body electronics) and is scheduled for introduction in safety-critical functions in the context of "by-wire systems". Among other issues systematic and accurate testing is therefore essential for establishing safety cases and is currently subject of intensive research. Traditional test methods are based on the generation of a stimulus (test vector) and the analysis of the resulting system reaction. Due to the low accessibility of the internal protocol mechanisms, embedded distributed systems usually provide additional local functionalities to enhance testability. Such methods, however, typically require additional resources and lead to interruption of normal services. The innovation of this project lies in the development of a framework to remotely apply given test vectors and analyze the system reaction transparently to the application. This transparency aims at (1) performing a non intrusive remote test based on generic (application independent), procedures, and (2) enabling test execution concurrent with normal system operation, thus increasing test coverage in making online tests possible. The context of this project is the TDMA scheme of modern distributed communication systems and the availability of a globally agreed time base achieved by a continuous correction of local clocks. The basic idea is to produce an identifiable bus traffic carrier which the nodes under test (NUT) have to synchronize to. Then, the analysis of the starting point of the messages transmitted by the NUT signalizes whether the carrier was correctly received (NUT stayed synchronous with the carriere) or not, and consequently provides information about the internal mechanisms that would not be available otherwise. The bus traffic carrier can be further coupled with state-of-the-art test vector generation approaches (such as proposed by the FIT-IT project STEACS) and thus enable systematic and transparent test of the communication services. Feasibility studies will be performed on a demonstrator setup to verify the concept.
People
Project leader
Andreas Steininger
(E182)
Project personnel
Eric Armengaud
(E182)
Institute
E182 - Institute of Computer Engineering
Grant funds
FFG - Österr. Forschungsförderungs- gesellschaft mbH (National)
Austrian Research Promotion Agency (FFG)
Research focus
Computer Engineering: 100%
Keywords
German
English
eingebettete Systeme
embedded systems
Steuergeräte im Auto
automotive controller
systematischer Test
systematic test
Publications
Publications