Asynchronous Logic in Real-Time Systems

01.12.2007 - 31.08.2011
Forschungsförderungsprojekt
Asynchronous circuit design techniques can provide economic solutions in cases where the traditional synchronous design is facing its limitations. Still, however, industry in general, and SMEs in particular, are reluctant to consider asynchronous design a viable alternative in these cases. There are several reasons for this, one prominent of these being the common belief that asynchronous logic is not suitable for real-time applications due to its apparently unpredictable temporal behaviour. Indeed, asynchronous circuits favourable ability to adapt its operating speed to the operating conditions at the same time translates into a variation of the (hardware) execution time for a given task. The central aim of this project is to perform a systematic investigation on whether this common apprehension is true or asynchronous design techniques are still suitable for real-time applications. The envisioned technical approach comprises the following three major steps: *) Since in fact the temporal behavior of asynchronous logic is not unpredictable but just more difficult to model than in the synchronous case, we will elaborate a precise timing model for asynchronous circuits that allows us to predict (at least a worst case of) its execution time for a given task. *) In many real-time applications a time reference is needed for communication, scheduling, timers etc. While this reference comes for free with the clock in a synchronous design, explicit measures are needed for this purpose in an asynchronous design. We shall propose and investigate appropriate solutions here as well. *) In order to guide our investigation by the actual needs of a practical application we use a TTP controller as our showcase. The controller for a time-triggered communication system is commonly accepted as a demanding real time design, therefore it is a tough benchmark for our approach that, if we can indeed accomplish its implementation in asynchronous logic, makes our results convincing. The project provides a unique opportunity to combine TTTech's expertise in time triggered architectures and the related controller design with the experience of TU Vienna's ECS group in asynchronous logic design.

Personen

Projektleiter_in

Projektmitarbeiter_innen

Institut

Grant funds

  • FFG - Österr. Forschungsförderungs- gesellschaft mbH (National) Austrian Research Promotion Agency (FFG)

Forschungsschwerpunkte

  • Computer Engineering: 100%

Schlagwörter

DeutschEnglisch
Asynchrone LogikAsynchronous Logic
Zeitliches VerhaltenTemporal Behavior

Publikationen