Person profile

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Andreas Steininger

Phone +43 1 58801 18251

E-Mailandreas.steininger@tuwien.ac.at

Assigned

E191-02	E056-17

Business Card

https://orcid.org/0000-0002-3847-1647

Research area

Name	Management/Member
Fachbereich Resilient Embedded Systems	Management
Fachbereich Trustworthy Autonomous Cyber-Physical Systems	Member
Forschungsbereich Embedded Computing Systems	Member

Profile

Research profile (German):

Asynchrone Logik, Fault Tolerant Clocking, Timing Domain Interfacing (Metastabilität), Fehlertolerante Rechenarchitekturen, Strahlungseffekte in Mikroelektronik, Fehlerinjektion, vertrauenswürdige Systeme, Technische Informatik

Research profile (English):

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics, Fault Injection, trustworthy systems, sustainable computing, computer engineering

Link to CV:

https://ti.tuwien.ac.at/ecs/people/steininger

Publications:

Publications

Keywords

Keyword (German)	Keyword (English)
Timing domain interfacing	Timing domain interfacing
Asynchrone Prozessoren	Clockless Processors
Computersysteme, hochzuverlässige	Dependable Computer Systems
Fehlererkennungsmechanismen, Hardware	Error Detection Mechanisms
Fehlertoleranz	Fault Tolerance
Rechnerarchitekturen	Computer Architecture
Built in Self Test (BIST)	Built in Self Test (BIST)

Research Focal Areas

Research focus	Research field	Keywords	Percentage
Information and Communication Technology	Computer Engineering and Software-Intensive Systems	Dependable Networked Embedded Systems, Fehlertolerante verteilte Echtzeitsysteme, Zeitgesteuerte Echtzeitsysteme, Dependable Systems-on-Chip, Model-based Design, Validation & Verification, Automation Systems, Speichersysteme	100

Faculty focus

Faculty focus	Percentage
ComputerEngineering	100

Area of expertise according to Statistik Austria

Code	Area of expertise (German)	Area of expertise (English)
2543	Entwurf integrierter Schaltungen	Integrated circuit design
2548	Sicherheit in der Informationstechnik (IT-Sicherheit)	IT security
2503	Computer Hardware, ADVA	Computer hardware, ADVA

Presidencies, assessments, or memberships in appointment/habilitation commissions

Committee type	Function	Candidate name	Committee location	from-to	Comment
Berufungskommission	Vorsitzende_r		Internal	05/2015 - 04/2016
Habilkommission	Mitglied		Internal	05/2010 - 10/2010

Journal participation

Title	Classification	Referenced	Function	From-To	Comment
E&I Elektrotechnik & Informationstechnik	unklassifiziert	Yes	Editor	06/2015 - 06/2015
Journal of Circuits, Systems, and Computers (JCSC)	SCI (Science Citation Index)	Yes	Associate Editor	03/2016 - 03/2016	Co-editor for special issue

Events / Conferences

Category	Collaboration	Event name	From	Until	Function/Comments
Postgraduale Lehrgänge/Summer School	Sonstiges		09/2008	09/2008	International Summer Academy 2008Design and Test Technology for Dependable Hardware / Sofrware SystemsBrandenburg University of Technology, CottbusVortrag über: Design and Test Technology for Automotive Electronic Systems
Postgraduale Lehrgänge/Summer School	Sonstiges		06/2011	06/2011	Lecture in CREDES Summer School on Dependable Systems Design
Wissenschaftliche Konferenz/Symposium	Organisator_in	IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2018)	05/2018	05/2018	General Chair
Wissenschaftliche Konferenz/Symposium	Organisator_in	IEEE International Conference on Design and Diagnostics on Electronic Circuits and Systems (DDECS 2010)	04/2010	04/2010	General Vice Chair
Wissenschaftliche Konferenz/Symposium	Organisator_in	IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2014)	05/2014	05/2014	Program Co-Chair
Wissenschaftliche Konferenz/Symposium	Organisator_in	IEEE International Conference on Design and Diagnostics on Electronic Circuits and Systems (DDECS 2016)			Program Co-Chair

Patents

Number	Title	Inventors	Date of First Patent Application	Publishing Links	Countries
AT20070001503	Verfahren zum Bestimmen des physikalischen Taktes eines Netzwerkknotens	TU Wien	04/2009	http://at.espacenet.com/public...
AT505804	Verfahren zum bestimmen des Taktverteilungsintervalles von Netzwerkknoten	TU Wien	09/2007	http://at.espacenet.com/search...