389.213 SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologies
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2022W, VO, 2.0h, 3.0EC

Properties

  • Semester hours: 2.0
  • Credits: 3.0
  • Type: VO Lecture
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to understand the software structure and required hardware that are necessary to physically design and operate a virtual coordinating twin and a number of real switching twins together with the interconnecting transmission links to become a real physical network in a production line network factory that can immediately be operated.  

The essential value of this course is to understand a completely new form of generalized networking by completely separating application and service flows from interconnection networking that is actually done by a two-plain SDN-Twin network with a single virtual coordination twin and a set of real network switching twins with their bidirectional control functionality. The real network twins report the network status, the virtual coordination or control twin continuously updates the actually status and react back when necessary such as aggregating a number of physical links to increase the link capacity. That is the twin software interaction principle, and in a sense rather straightforward. Open real-hardware flexible implementations that can be controlled freely, needs other methods than just exchanging commands or messages between twins. Today, advances in CPU/GPU/DPU processing and memory hierarchy technologies to realize switching nodes, the switching twins, completely in computing technology using CUDA, PCIe, NVMe, CXL, RoCE and MTM switching as software methods in connection with all transmission technologies that exist.  

CPU (central), GPU (graphic), DPU (data center), CUDA (compute unified device architecture), PCIe (peripheral component interconnect express), NVMe (non-volatile memory express), CXL (compute express link), RoCE (RDMA over converged Ethernet), MTM (memory transfer mode).

Subject of course

SDN-Twin software and hardware methods and design

Teaching methods

Lecture with discussion and joined leaning from new insights in the small SDN-Twin semester projects assigned to students that want to take an exam.

Mode of examination

Oral

Additional information

Slides and suffient additional information


Lecturers

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Institute

Course dates

DayTimeDateLocationDescription
Thu17:00 - 19:0006.10.2022 - 26.01.2023EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologies - Single appointments
DayDateTimeLocationDescription
Thu06.10.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu13.10.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu20.10.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu27.10.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu03.11.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu10.11.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu17.11.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu24.11.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu01.12.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu15.12.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu22.12.202217:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu12.01.202317:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu19.01.202317:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess
Thu26.01.202317:00 - 19:00EI 6 Eckert HS SDN-Twin CPU/GPU/DPU processing with memory hierarchy and transmission technologiess

Examination modalities

Software-defined-networking with digital twins is a complete new way of networking for many kinds of networks. Teaching this new method can only be effective when at least all major issues are addressed. There must be a fast and steep learning curve. This new topic is covered in a set of optional lectures for which one can collect additional credits. In the Master and PhD programs, there is not a need to collect so many credits. In fact, this is a complete special topic study embedded in a collection of voluntary lectures. In order that attendees interested to be trained in all aspects of SDN-Twin networks can profit, an appropriate mode of examination will be introduced.

The examination will be performed as special examination events with additional audience in lecture room EI 7 during lecture-free days after and before a semester. In addition, also such events in smaller rooms will be organized on request. Both in WS and SS there are SDN-Twin lectures. On the SDN-Twin homepage, additional information will be available to prepare for the examination  questions. In each semester, candidates can take an exam for up to 4 visited lectures with an assigned topic consisting of a written report (about 20 pages), a presentation (20 minutes) and answering questions on the content of the lectures indicated in the exam registration (10 minutes). Each visited optional lecture will be honoured by 3 ECTS, so that also all surplus optional lectures will appear as certificate for the special SDN-Twin education. Of course listeners are welcome to attend all examination events.

Course registration

Not necessary

Curricula

Study CodeObligationSemesterPrecon.Info
710 FW Elective Courses - Electrical Engineering Not specified

Literature

No lecture notes are available.

Previous knowledge

New way of IP and Internet-of-things networking since SDN-Twin is purely based on CPU/GPU/DPU processing with memory hierarchy and transmission technologies. Therefore, current networking knowledge is helpful but not much relevant. With respect to informatics courses, SDN-Twin will be an important case to be aware of.

Accompanying courses

Miscellaneous

Language

English