389.185 Lab FPGA Programming Fundamentals using VHDL
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2020S, LU, 2.0h, 2.0EC
This course is evaluated following the new mode. Learn more

Course evaluation


  • Semester hours: 2.0
  • Credits: 2.0
  • Type: LU Laboratory Exercise

Learning outcomes

After successful completion of the course, students are able to design FPGA designs independently and develop the corresponding VHDL code. In addition, topics as timing, energy consumption, ... are discussed too. 

Subject of course

  • Aufbau eines PLD (Programmable Logic Device)

  • Xilinx ISE Software

  • VHDL Entities/Architectures

  • VHDL Testbench

  • Programmiersprache VHDL

  • Timing/Metastabilitäten 

Teaching methods

The lecture is divided into several exercises. Each exercise covers a specific area of the script. After a short theoretical part, the theory is tested on a FPGA board. 

Mode of examination

Written and oral

Additional information

Voraussetzungen: Kenntnisse der Grundlagen der Elektrotechnik und der Programmierung

Zielgruppe: Studierende im Doktoratsstudium sowie im Bachelor- und Masterstudium Telekommunikation sowie verwandter Fachgebiete in Elektrotechnik und Informatik 

Termine: Di 9:30-11:30 Raum: CG 0210

Erste Vorlesung: Di., 3.3.2020

Leistungsnachweis: Laborübungen, Protokoll(e) 

Literatur: Es wird ein Skriptum zum download angeboten.

Sprache: Deutsch 





Examination modalities

Half ot the points are achieved with the individual exercises (where the exercise number equals the maximum points for the exercise), the other half is for a final project. For this project also own suggestions can be introduced. 

Course registration

Begin End Deregistration end
04.01.2020 00:01 16.03.2020 23:59 30.03.2020 23:59

Registration modalities:

Sie benötigen einen Laptop. Sollten Sie keinen eigenen Laptop besitzen und können sich auch keinen ausborgen kontaktieren Sie mich bitte. 



No lecture notes are available.


  • Attendance Required!