384.178 SoC Design Lab
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2021W, UE, 4.0h, 6.0EC

Properties

  • Semester hours: 4.0
  • Credits: 6.0
  • Type: UE Exercise
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to practice various procedures of designing a System on Chip. The architecture design, IP purchase, (FPGA) implementation flow. Beside introducing some hardware verification concepts to be applied during the development of projects.

Introduction to System Verilog and practicing system Verilog assertions and industrial standard verification technologies like OVM and UVM.

Students will aslo be introduced to ASIC desgn flow and practice some hands-on exercises.

Subject of course

- SoC Design project in groups is implemented during the semester and submitted middle of March.

-          Hardware verification domain

  • Introduction to formal Hardware verification
  • Functional verification in the design cycle

- Hardware verification tools and methodologies

  • Verification Environment
  • Metric Driven Verification Planning
  • Metrics Definition and Collection
  • Monitors and Checkers
  • Verification Closure
  • Automated test generation

-  System Verilog Assertions

- Industrial standard verification technologies

  • Universal Verification Methodology (UVM)
  • Open Verification Methodology(OVM)
  • Verification Methodology Manual(VMM)

- ASIC Design Flow

Teaching methods

Practical Projects

Presentations

Lab exercises

Mode of examination

Oral

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Tue12:00 - 13:0005.10.2021 https://tuwien.zoom.us/j/9510952108?pwd=eDMzanBvamMxVnljeStDa0JuSHYzUT09 (LIVE)Introuductory Session
Tue12:00 - 14:0012.10.2021 https://tuwien.zoom.us/j/9510952108?pwd=eDMzanBvamMxVnljeStDa0JuSHYzUT09 (LIVE)Introduction to Hardware Verification
Tue12:00 - 13:0019.10.2021 https://tuwien.zoom.us/j/9510952108?pwd=eDMzanBvamMxVnljeStDa0JuSHYzUT09 (LIVE)Project groups and Abstract submission
Tue12:00 - 14:0009.11.2021 System Verilog (LIVE)System Verilog
Tue12:00 - 14:0016.11.2021 https://tuwien.zoom.us/j/9510952108?pwd=eDMzanBvamMxVnljeStDa0JuSHYzUT09 (LIVE)System Verilog Assertions
Tue13:00 - 16:0023.11.2021 https://tuwien.zoom.us/j/9510952108?pwd=eDMzanBvamMxVnljeStDa0JuSHYzUT09 (LIVE)First Mid-term Project Presentation
Tue13:00 - 16:0011.01.2022 https://tuwien.zoom.us/j/9510952108?pwd=eDMzanBvamMxVnljeStDa0JuSHYzUT09 (LIVE)Second mid-term Project presentation
Tue11:00 - 15:0008.03.2022 Computer Room - CA0208Final Project Demo

Examination modalities

Practical Projects

Presentations

Group dates

GroupDayTimeDateLocationDescription
Group ATue09:00 - 11:3007.12.2021 System Verilog exercises in Computer Room CA0208384.178 SoC Design Lab Group A
Group ATue09:00 - 11:3014.12.2021 System Verilog exercises in Computer Room CA0208384.178 SoC Design Lab Group A
Group ATue09:00 - 11:3018.01.2022 ASIC Design flow in Computer Room CA0208384.178 SoC Design Lab Group A
Group ATue09:00 - 11:3025.01.2022 ASIC Design flow in Computer Room CA0208384.178 SoC Design Lab Group A
Group BTue12:00 - 14:3007.12.2021 System Verilog exercises in Computer Room CA0208384.178 SoC Design Lab Group B
Group BTue12:00 - 14:3014.12.2021 System Verilog exercises in Computer Room CA0208384.178 SoC Design Lab Group B
Group BTue12:00 - 14:3018.01.2022 ASIC Design flow in Computer Room CA0208384.178 SoC Design Lab Group B
Group BTue12:00 - 14:3025.01.2022 ASIC Design flow in Computer Room CA0208384.178 SoC Design Lab Group B
Group CTue15:00 - 17:3007.12.2021 System Verilog exercises in Computer Room CA0208384.178 SoC Design Lab Group C
Group CTue15:00 - 17:3014.12.2021 System Verilog exercises in Computer Room CA0208384.178 SoC Design Lab Group C
Group CTue15:00 - 17:3018.01.2022 ASIC Design flow in Computer Room CA0208384.178 SoC Design Lab Group C
Group CTue15:00 - 17:3025.01.2022 ASIC Design flow in Computer Room CA0208384.178 SoC Design Lab Group C

Course registration

Begin End Deregistration end
05.10.2021 16:00 26.10.2021 20:00 26.10.2021 20:00

Group Registration

GroupRegistration FromTo
Group A26.10.2021 13:0012.11.2021 12:00
Group B26.10.2021 13:0012.11.2021 12:00
Group C26.10.2021 13:0007.11.2021 12:00
P1:Formal Verification for GPUs13.10.2021 10:3019.10.2021 14:00
P2: Dynamic Reconfiguration IOT device13.10.2021 10:3019.10.2021 14:00
P3 Reliability management of modular FPGA applications13.10.2021 10:3019.10.2021 14:00
P4: Accuracy of approximate circuits13.10.2021 10:3019.10.2021 14:00
P5: Integration of an encryption coprocessor into an open-source low-power microcontroller (PULPissimo)13.10.2021 11:0019.10.2021 14:00
P6: Dynamic Reconfiguration of different IoT device protocols17.10.2021 12:00

Curricula

Study CodeObligationSemesterPrecon.Info
066 504 Master programme Embedded Systems Mandatory

Literature

No lecture notes are available.

Preceding courses

Language

English