After successful completion of the course, students are able to practice various procedures of designing a System on Chip. The architecture design, IP purchase, (FPGA) implementation flow. Beside introducing some hardware verification concepts to be applied during the development of projects.

Introduction to System Verilog and practicing system Verilog assertions and industrial standard verification technologies like OVM and UVM.

Students will aslo be introduced to ASIC desgn flow and practice some hands-on exercises.

- SoC Design project in groups is implemented during the semester and submitted middle of March.

-          Hardware verification domain (1 Week)

• Introduction to formal Hardware verification
• Functional verification in the design cycle

- Hardware verification tools and methodologies (2 Weeks)

• Verification Environment
• Metric Driven Verification Planning
• Metrics Definition and Collection
• Monitors and Checkers
• Verification Closure
• Automated test generation

-  System Verilog Assertions (3 Week)

- Industrial standard verification technologies (1 Weeks)

• Universal Verification Methodology (UVM)
• Open Verification Methodology(OVM)
• Verification Methodology Manual(VMM)

- ASIC Design Flow (6 Weeks)

Practical Projects

Presentations

Lab exercises

Practical Projects

Presentations