384.154 Embedded Systems in FPGAs
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2022S, VU, 3.0h, 4.5EC

Properties

  • Semester hours: 3.0
  • Credits: 4.5
  • Type: VU Lecture and Exercise
  • Format: Presence

Learning outcomes

After successful completion of the course, students are able to understand the basic concepts of modeling, simulation, design methodologies of embedded systems. For more details, please ask the lecturer.

Subject of course

modeling, simulation, design of embedded systems.

Teaching methods

Lecture slides and relevant literature references

The medium of communication is English

Mode of examination

Immanent

Additional information

The lectures on Embedded Systems in FPGA (SS2022) will be conducted every Wednesday, starting from 23.03.2022 until 15.06.2022 from 15:30-17:00 in EI 8 Pötzl HS - QUER

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Wed15:00 - 17:0023.03.2022 - 29.06.2022EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Embedded Systems in FPGAs - Single appointments
DayDateTimeLocationDescription
Wed23.03.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed30.03.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed06.04.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed27.04.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed04.05.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed11.05.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed18.05.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed25.05.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed01.06.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed08.06.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed15.06.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed22.06.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA
Wed29.06.202215:00 - 17:00EI 8 Pötzl HS - QUER Embedded Systems in FPGA

Examination modalities

Written Exam for the lectures: (contact: semeen.rehman@tuwien.ac.at)

Lab: (contact : severin.jaeger@tuwien.ac.at ; semeen.rehman@tuwien.ac.at)

Labs: There are 2 Lab projects: SystemC and ZynQ. Interviews about the solutions will take place.

Course registration

Begin End Deregistration end
28.02.2022 08:00 22.03.2022 23:00 22.03.2022 23:00

Curricula

Literature

No lecture notes are available.

Previous knowledge

Design of digital circuits and systems

Circuit design using VHDL

Basic knowledge in modeling and simulation

Testing and verification of digital hardware circuits

Programming language C/C++

Language

English