After successful completion of the course, students are able to understand the basic concepts of modeling, simulation, design methodologies of embedded systems. For more details, please ask the lecturer.
modeling, simulation, design of embedded systems.
Lecture slides with iterature references
Tools for the Lab projects The medium of communication is English
The lectures on Embedded Systems in FPGA (SS2020) will be conducted every Wednesday from 09:30-11:00 in Seminarraum 127 (EEIT, Gußhausstraße 27-29,1040 Vienna). The lectures will start on 11.03.2020.
Addtional details will be presented in the first session.
Written Exam (contact : semeen.rehman@tuwien.ac.at)
Labs (contact: saeed.seyedfaraji@tuwien.ac.at ; semeen.rehman@tuwien.ac.at)
Lab Part 1: Four Tasks for SystemC.
Lab Part 2: Four Tasks for ZynQ.
QnA about the solutions for both the SystemC and ZynQ lab tasks
Design of digital circuits and systems
Circuit design using VHDL
Basic knowledge in modeling and simulation
Testing and verification of digital hardware circuits
Programming language C/C++