384.088 Digital Integrated Circuits Laboratory
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2022S, UE, 2.0h, 3.0EC
TUWEL

Properties

  • Semester hours: 2.0
  • Credits: 3.0
  • Type: UE Exercise
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to design and verify digitial integrated circuits in a team using state-of-the-art methods, and to package a design for re-usability and maintainance.

Subject of course

  1. Describe the solution to a problem in a behavioral HDL
  2. Learn to use the code of others
  3. Learn what is important by using code of others: licensing, coding style, integration to your own code base
  4. Create a self-contained package along with information necessary to be used by others
  5. Learn to use several design tools for simulation and synthesis: Yosys, nextpnr, GHDL, GTKWave
  6. Learn to automate tasks by scripting (Bash scripts, Makefiles, TCL scripts, ...)
  7. Learn to collaborate, and to use tools that support collaboration (git, Telegram, ...)
  8. Learn that it is not important to solve any problem strictly on your own, but that it is important to collaborate and to communicate in order to solve big problems
  9. Learn that specifications never are complete (and that communication is important to make them complete for a limited scope)
  10. Learn about licensing your own work

Teaching methods

In the lab we will concuct a digital hardware design project in a team. The goal is to implement a specification, and to prove the implementation's correctness with formal verification methods.

Collaboration between colleagues is not only allowed, but encouraged. It is, however, not allowed to simply copy a design without knowing what is going on. This will be checked in the lab reviews.

Mode of examination

Immanent

Additional information

In the case of more registrations than places, students with an active relevant master degree (066 438, 066 439, 066 504, 066 507 and 066 508) are preferably admitted to students of other subjects. Within these groups the lot decides on the allocation of the space.

In order to foster cooperation in the team, we aim at having the course in presence at the institute. Depending on infection numbers we will switch to Zoom accordingly.

Due to the current infection numbers, we will give the introduction on March 4 via Zoom, so that ill and/or quarantined students are able to join as well. Due to this reason, we will continue having Zoom sessions until March 25.

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Fri10:00 - 14:0004.03.2022 - 17.06.2022 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09 (LIVE)Support Session
Digital Integrated Circuits Laboratory - Single appointments
DayDateTimeLocationDescription
Fri04.03.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri11.03.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri18.03.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri25.03.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri01.04.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri08.04.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri29.04.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri06.05.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri13.05.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri20.05.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri03.06.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri10.06.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session
Fri17.06.202210:00 - 14:00 Computerraum CA0208 / Zoom: https://tuwien.zoom.us/j/96695763333?pwd=eTJpcFQ1MFhUSmpaSVVCeEFOelh3QT09Support Session

Examination modalities

Continuous evaluation. Evaluation criteria are:

  1. Understanding the implemented task
  2. The solution's elegance
  3. Group activity
  4. Willingness to collaborate
  5. Conformance to formal requirements

 

Course registration

Begin End Deregistration end
24.02.2022 00:00 11.03.2022 00:00 18.03.2022 15:00

Curricula

Literature

Lecture notes for this course are available. The actual versions can be accessed over TISS.

Previous knowledge

Knowledge in the following areas is advantageous:

  1. Hardware description languages: VHDL, Verilog, SystemVerilog ASsertions (SVA), C++, Python, Bash
  2. Formal modelling languages: SystemVerilog
  3. EDA concepts: Modelling, synthesis, optimization, technology mapping, timing analysis, functional simulation, etc.
  4. EDA tools: Yosys, nextpnr, icetime, Icarus Verilog, GHDL
  5. Good understanding of digital system design, computer architecture

Miscellaneous

  • Attendance Required!

Language

English