384.088 Digital Integrated Circuits Laboratory
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2019S, UE, 2.0h, 3.0EC
TUWEL

Properties

  • Semester hours: 2.0
  • Credits: 3.0
  • Type: UE Exercise

Aim of course

LDIS starts 12th of March, 2019 08:00 AM, in the ICT's computer lab (CA0208)

This lecture serves the following goals:

  1. Synthesis: Understand a standard hardware synthesis flow (target architecture: FPGA)
  2. Verification: Learn to use functional verification in order to debug hardware designs
  3. Investigation: Learn methods to understand a given hardware design

Subject of course

There will be a theortetical part to introduce concepts that are important for integrated circuit design, and to present tools that can be used to accomplish the lab tasks. Students are free to use any tool chain and language they want. However, support is only given for tools and languages that are presented during the theoretical part of the lab.

The practical part is divided into three tasks with increasing complexity. There will be three deadlines to finish the tasks, and there will be reviews and presentations to check the learning achievements.

Collaboration between colleagues is not only allowed, but encouraged. It is, however, not allowed to simply copy a design without knowing what is going on. This will be checked in the lab reviews.

 

Additional information

In the case of more registrations than places, students with an active relevant master degree (066 438, 066 439, 066 504, 066 507 and 066 508) are preferably admitted to students of other subjects. Within these groups the lot decides on the allocation of the space.

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Tue08:00 - 12:0012.03.2019 - 25.06.2019 Computer room ICT CA0208LDIS
Tue08:00 - 12:0009.04.2019Seminarraum 384 LDIS
Tue10:00 - 12:0009.04.2019 Rechnerraum ICT CA0208LDIS
Digital Integrated Circuits Laboratory - Single appointments
DayDateTimeLocationDescription
Tue12.03.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue19.03.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue26.03.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue02.04.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue09.04.201908:00 - 12:00Seminarraum 384 LDIS
Tue09.04.201910:00 - 12:00 Rechnerraum ICT CA0208LDIS
Tue30.04.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue21.05.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue04.06.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue18.06.201908:00 - 12:00 Computer room ICT CA0208LDIS
Tue25.06.201908:00 - 12:00 Computer room ICT CA0208LDIS

Examination modalities

Continuous evaluation. Evaluation criteria are:

  1. Understanding the implemented task
  2. The solution's elegance
  3. Conformance to formal requirements

Please submit your solutions during the lab times at the ICT's computer room. If you would like to submit your solutions beyond lab times, please agree on an appointment with the course management.

Course registration

Begin End Deregistration end
01.03.2019 00:00 22.03.2019 12:00 22.03.2019 12:00

Curricula

Literature

Lecture notes for this course are available. The actual versions can be accessed over TISS.

Previous knowledge

Knowledge in the following areas is advantageous:

  1. Hardware description languages like VHDL and/or Verilog
  2. Good understanding of digital system design, computer architecture

Language

English