This lecture serves the following goals:

1. Synthesis: Understand a standard hardware synthesis flow (target architecture: FPGA)
2. Verification: Learn to use functional verification in order to debug hardware designs
3. Investigation: Learn methods to understand a given hardware design

There will be a theortetical part to introduce concepts that are important for integrated circuit design, and to present tools that can be used to accomplish the lab tasks. Students are free to use any tool chain and language they want. However, support is only given for tools and languages that are presented during the theoretical part of the lab.

The practical part is divided into three tasks with increasing complexity. The tasks are to be accomplished in groups of two students. There will be three deadlines to finish the tasks, and there will be reviews to check the learning achievements.

Collaboration between groups is not only allowed, but encouraged. It is, however, not allowed to simply copy a design without knowing what is going on. This will be checked in the lab reviews.

In the case of more registrations than places, students with an active relevant master degree (066 438, 066 439, 066 504, 066 507 and 066 508) are preferably admitted to students of other subjects. Within these groups the lot decides on the allocation of the space.

Continuous evaluation. Evaluation criteria are:

1. Understanding the implemented task
2. The solution's elegance
3. Conformance to formal requirements

Please submit your solutions during the lab times at the ICT's computer room. If you would like to submit your solutions beyond lab times, please agree on an appointment with the course management.

Lecture notes for this course are available. The actual versions can be accessed over TISS.

Knowledge in the following areas is advantageous:

1. Hardware description languages like VHDL and/or Verilog
2. Good understanding of digital system design, computer architecture