384.086 Digital Integrated Circuits
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2023W, VU, 2.0h, 3.0EC


  • Semester hours: 2.0
  • Credits: 3.0
  • Type: VU Lecture and Exercise
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to

-  Explain the ASIC and FPGA design process;

-  Demonstrate important synthesis algorithm such as logic synthesis and technology mapping;

-  Model, validate and implement simple designs on FPGAs;

-  Discuss the simulation and synthesis semantics of an HDL (VHDL or Verilog);

-  Design, simulate and validate HDL models for netlists, dataflow, processes and algorithms.

Subject of course

The course is based on the text book "Taking AIMS at Digital Design" by A. Jantsch. There is a link to the digital version of the book (see 'Litereature'). Additionally, all enrolled students can download lecture slides and supplimentary material in the course's download section.

The covered topics are: Modeling of digital circuits, a Hardware Description Langauge (HDL), logic optimization, mapping and implementation of digital design models, datapath models, Latches, Flip-Flops and Registers, synchronous design, synchronization, programmable logic, and other topcis of digital design.

Teaching methods

This year the class will be conducted in hybrid mode.

The theory will be studied before and during consolidation sessions and the practical skills will be acquired by solving practical examples in associated exercises.

Consolidation Sessions in the lecture room (or on-line)

The consodliation sessions are in the leture room or, if necessary, on-line. We use TUWEL as platform (and possibly Zoom).

All the course material, slides, and complementary material, will be provided in TUWEL.
Students prepare for the consolidation sessions by studying the material and formulating questions, which are then answered and discussed during the consolidation sessions.
For at least 80% of the sessions at least one question has to be formulated at least 24 hours bevore the corresponding session.


The exercise consists of two parts:

  1. Design-time part: You model and verify a simple design and transform it into an FPGA bitstream step-by-step
  2. Run-time part: You run and verify your simple design on an FPGA platform

As HDL we use Verilog.

The exercises part will be fully held as a distance learning format. We'll have weekly video support sessions via Zoom (2h each), and e-mail support.

Mode of examination

Written and oral

Additional information

You must be enrolled to the course; this will entitle you to download the slides and to do the exercises (please note that you have to enroll to separate groups for the exercises).

This course is part of the Embedded Systems master program, in particular part of the SoC track. The Institute of Computer Technology offers several other relevant courses.

ECTS distribution:

15h ...   Participation in the consolidation sessions
12h ...   Preperation for the consolidation sessions
18h ...   VELS/Simulation exercises
10h ...   Labs
20h ...   Preparation for the exam
75h ...  3 ECTS credits in total



Course dates

Tue09:00 - 11:0003.10.2023 - 23.01.2024EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu13:30 - 14:3005.10.2023 - 07.12.2023 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09 (LIVE)Video support session
Digital Integrated Circuits - Single appointments
Tue03.10.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu05.10.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue10.10.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu12.10.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue17.10.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu19.10.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue24.10.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Tue31.10.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Tue07.11.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu09.11.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue14.11.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu16.11.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue21.11.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu23.11.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue28.11.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu30.11.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue05.12.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu07.12.202313:30 - 14:30 https://tuwien.zoom.us/j/68397099090?pwd=V3BDcFlYVlk1T3NDZHRiMExmaUJlQT09Video support session
Tue12.12.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Tue19.12.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation

Examination modalities

Consolidation Sessions

 As preperation for consolidation sessions students must prepare in the corresponding TUWEL forum

  • for at least 80% of the sessions
  • at least one subject-specific and meaningful question
  • at least 24 hours before the corresponding session.

I.e. if there are ten sessions, eight questions must be formulated at the very minimum.

The timely formulation of the minimum number of questions is a requirement for passing the exercise part of the class.


  1. 7 VELS/simulation examples: 7 points each -> 49 points
  2. 1 FPGA lab: 51 points

You must at least get 51 points for the exercises to be entitled to do the exam.
Surplus points 52-100 will contribute to your final grade (max 49 points).


Exams will be held written or orally. The exam's mode is specific for a given exam date and will be announced in TISS.
You can only do an exam if you successfully passed the exercises.

You are allowed to use any printed material and a calculator, but no PC or laptop.

For the exam, you can get max 100 points.


The grading depends on the acquired points from exercises and exam. In total, you can get max 149 points.

0-74 points -> N5

75-93 points -> G4

94-112 points -> B3

113-131 points -> U2

132-149 points -> S1


DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Mon15:00 - 18:0011.11.2024 Büro Jantschoral21.10.2024 12:00 - 07.11.2024 23:59TISSDIS Prüfung (Stoff WS 2021)
Mon16:00 - 19:0016.12.2024 Büro Jantschoral25.11.2024 12:00 - 12.12.2024 23:59TISSDIS Prüfung (Stoff WS 2021)
Tue09:00 - 11:0014.01.2025EI 8 Pötzl HS - QUER written17.12.2024 06:00 - 09.01.2025 23:59TISSDIS Prüfung (Stoff WS23)
Mon15:00 - 16:3024.02.2025 Officce Jantschoral15.01.2025 12:00 - 16.02.2025 23:59TISSDIS Prüfung (Stoff WS 2023)
Tue16:00 - 18:0004.03.2025EI 11 Geodäsie HS - GEO written04.02.2025 12:00 - 28.02.2025 23:59TISSDIS Prüfung (Stoff WS 2023)
Mon16:00 - 18:0021.04.2025 Büro Jantschoral29.03.2025 11:00 - 10.04.2025 23:59TISSDIS Prüfung (Stoff WS 2023)
Mon15:00 - 17:0012.05.2025 Büro Jantschoral14.04.2025 23:59 - 08.05.2025 23:59TISSDIS Prüfung (Stoff WS 2023)

Course registration

Begin End Deregistration end
31.08.2023 12:00 08.10.2023 12:00 08.10.2023 12:00


Study CodeObligationSemesterPrecon.Info
066 438 Computer Technology Not specified1. Semester
066 439 Microelectronics Not specified1. Semester
066 504 Master programme Embedded Systems Mandatory1. Semester
066 507 Telecommunications Mandatory
066 508 Microelectronics and Photonics Mandatory1. Semester


Axel Jantsch, Taking AIMS at Digital Design, Springer, 2023. (Accessible from inside the TU Nnetwork)

Continuative courses


if required in English