384.086 Digital Integrated Circuits
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2021W, VU, 2.0h, 3.0EC
TUWEL

Properties

  • Semester hours: 2.0
  • Credits: 3.0
  • Type: VU Lecture and Exercise
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to

-  Explain the ASIC and FPGA design process;

-  Demonstrate important synthesis algorithm such as logic synthesis and technology mapping;

-  Model, validate and implement simple designs on FPGAs;

-  Discuss the simulation and synthesis semantics of an HDL (VHDL or Verilog);

-  Design, simulate and validate HDL models for netlists, dataflow, processes and algorithms.

Subject of course

The course is based on the text book "Lehrbuch Digitaltechnik" by Jürgen Reichardt. There is a link to the digital version of the book (see 'Litereature'). Additionally, all enrolled students can download lecture slides and supplimentary material in the course's download section.

The covered topics are: Modeling of digital circuits, a Hardware Description Langauge (HDL), logic optimization, mapping and implementation of digital design models, datapath models, Latches, Flip-Flops and Registers, synchronous design, synchronization, programmable logic, and other topcis of digital design.

Teaching methods

This year the class will be conducted in hybrid mode.

The theory will be studied before and during consolidation sessions and the practical skills will be acquired by solving practical examples in associated exercises.

Consolidation Sessions

The consodliation sessions are online or in the lecture room. We use Zoom and TUWEL.

All the course material, slides, video clips and complementary material, will be provided in TUWEL.
Students prepare for the consolidation sessions by studying the material and formulating questions, which are then answered and discussed during the consolidation sessions.
For at least 80% of the sessions at least one question has to be formulated at least 24 hours bevore the corresponding session.

Exercises

The exercise consists of two parts:

  1. Design-time part: You model and verify a simple design and transform it into an FPGA bitstream step-by-step
  2. Run-time part: You run and verify your simple design on an FPGA platform

As HDL we use Verilog.

The exercises part will be fully held as a distance learning format. We'll have weekly video support sessions via Zoom (2h each), and e-mail support.

Mode of examination

Written and oral

Additional information

You must be enrolled to the course; this will entitle you to download the slides and to do the exercises (please note that you have to enroll to separate groups for the exercises).

This course is part of the Embedded Systems master program, in particular part of the SoC track. The Institute of Computer Technology offers several other relevant courses.

ECTS distribution:

15h ...   Participation in the consolidation sessions
12h ...   Preperation for the consolidation sessions
18h ...   VELS/Simulation exercises
10h ...   Labs
20h ...   Preparation for the exam
---------------
75h ...  3 ECTS credits in total

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Tue09:00 - 11:0005.10.2021 - 25.01.2022 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09 (LIVE)Lectrue & Consolidation
Thu11:00 - 13:0007.10.2021 - 09.12.2021 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281 (LIVE)Video Support Session
08:00 - 16:0013.12.2021 - 17.12.2021 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Lab week
Digital Integrated Circuits - Single appointments
DayDateTimeLocationDescription
Tue05.10.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu07.10.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue12.10.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu14.10.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue19.10.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu21.10.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue09.11.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu11.11.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue16.11.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu18.11.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue23.11.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu25.11.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue30.11.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu02.12.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Tue07.12.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Thu09.12.202111:00 - 13:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Video Support Session
Mon13.12.202108:00 - 16:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Lab week
Tue14.12.202108:00 - 16:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Lab week
Tue14.12.202109:00 - 11:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281?pwd=c2M3NDFCVzUralg3Ni8yQVYvQkh6dz09Lectrue & Consolidation
Wed15.12.202108:00 - 16:00 Zoom Meeting Id: 996 2453 0281 https://tuwien.zoom.us/j/99624530281Lab week

Examination modalities

Consolidation Sessions

 As preperation for consolidation sessions students must prepare in the corresponding TUWEL forum

  • for at least 80% of the sessions
  • at least one subject-specific and meaningful question
  • at least 24 hours before the corresponding session.

I.e. if there are ten sessions, eight questions must be formulated at the very minimum.

The timely formulation of the minimum number of questions is a requirement for passing the exercise part of the class.

Exercises

  1. 7 VELS/simulation examples: 10 points each -> 70 points
  2. 1 FPGA lab: 30 points

You must at least get 51 points for the exercises to be entitled to do the exam.
Surplus points 52-100 will contribute to your final grade (max 49 points).

Exam

Exams will be held written or orally. The exam's mode is specific for a given exam date and will be announced in TISS.
You can only do an exam if you successfully passed the exercises.

You are not allowed to use any material (not even a calculator).

For the exam, you can get max 100 points.

Grading

The grading depends on the acquired points from exercises and exam. In total, you can get max 149 points.

0-74 points -> N5

75-93 points -> G4

94-112 points -> B3

113-131 points -> U2

132-149 points -> S1

Course registration

Begin End Deregistration end
27.09.2021 10:45 10.10.2021 23:59 10.10.2021 23:59

Registration modalities

Registration is necessary to successfully complete the course, to download the slides and attend the labratories.

Curricula

Literature

Reichardt, Jürgen, Lehrbuch Digitaltechnik, Oldenbourg Verlag, 2013.

Kesel, Frank / Bartholomä, Ruben, Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs, Oldenbourg Verlag, 2013

Continuative courses

Language

if required in English