After successful completion of the course, students are able to

-  Explain the ASIC and FPGA design process;

-  Demonstrate important synthesis algorithm such as logic synthesis and technology mapping;

-  Model, validate and implement simple designs on FPGAs;

-  Discuss the simulation and synthesis semantics of an HDL (VHDL or Verilog);

-  Design, simulate and validate HDL models for netlists, dataflow, processes and algorithms.

The lecture is based on the text book "Lehrbuch Digitaltechnik" by Jürgen Reichardt. There is a link to the digital version of the book (see 'Litereature'). Additionally, all enrolled students can download lecture slides and supplimentary material in the course's download section.

The covered topics are: Modeling of digital circuits, VHDL, logic optimization, mapping and implementation of digital design models, datapath models, Latches, Flip-Flops and Registers, synchronous design, synchronization, programmable logic, and other topcis of digital design.

The theory will be given in the lecture and will be consolidated by solving practical examples in an associated exercise.

The exercise consists of two parts:

1. Design-time part: You model and verify a simple design and transform it into an FPGA bitstream step-by-step
2. Run-time part: You run and verify your simple design on an FPGA platform

As HDL we use VHDL and Verilog.

You must be enrolled to the course; this will entitle you to download the slides and to do the exercises (please note that you have to enroll to separate groups for the exercises).

This course is part of the Embedded Systems master program, in particular part of the SoC track. The Institute of Computer Technology offers several other relevant courses.

ECTS share:

26h ...   Participation in the lecture and exercises
10h ...   VELS/Simulation exercises
18h ...   Labs
21h ...   Preparation for the exam
---------------
75h ...  3 ECTS credits in total

Exams will be held written or orally. The exam's mode will be given at the respective exam date. You can only do an exam if you successfully passed the exercises.

You are not allowed to use any material (not even a calculator).

Exercises:

1. 8 VELS/simulation examples: 6.25 points each -> 50 points
2. 2 FPGA labs: 25 points each -> 50 points

You must at least get 51 points for the exercises to be entitled to do the exam.
Surplus points 52-100 will contribute to your final grade (max 49 points).
For the exam, you can get max 100 points. In total, you can get max 149 points.

0-74 points -> N5

75-93 points -> G4

94-112 points -> B3

113-131 points -> U2

132-149 points -> S1

Registration is necessary to successfully complete the course, to download the slides and attend the labratories.

Reichardt, Jürgen, Lehrbuch Digitaltechnik, Oldenbourg Verlag, 2013.

Kesel, Frank / Bartholomä, Ruben, Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs, Oldenbourg Verlag, 2013