354.064 Advanced Course Circuit Design
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2016W, VU, 4.0h, 6.0EC, to be held in blocked form

Properties

  • Semester hours: 4.0
  • Credits: 6.0
  • Type: VU Lecture and Exercise

Aim of course

advanced knowledge of analog integrated circuit design

Subject of course

Design and layout of an IC with Cadence

Design for Testability

Additional information

Termine für die VO Design for Testability  werden in der Vorbesprechung vereinbart.

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Tue13:15 - 17:0018.10.2016 - 06.12.2016 Labor 1Cadence Labor
Mon13:15 - 17:0007.11.2016 Sem. 354Vorlesungsteil
Advanced Course Circuit Design - Single appointments
DayDateTimeLocationDescription
Tue18.10.201613:15 - 17:00 Labor 1Cadence Labor
Tue25.10.201613:15 - 17:00 Labor 1Cadence Labor
Mon07.11.201613:15 - 17:00 Sem. 354Vorlesungsteil
Tue08.11.201613:15 - 17:00 Labor 1Cadence Labor
Tue22.11.201613:15 - 17:00 Labor 1Cadence Labor
Tue29.11.201613:15 - 17:00 Labor 1Cadence Labor
Tue06.12.201613:15 - 17:00 Labor 1Cadence Labor
Course is held blocked

Course registration

Begin End Deregistration end
08.09.2016 00:00 07.10.2016 00:00 07.10.2016 00:00

Precondition

The student must have at least 1 of the course(s) completed listed below:

Curricula

Study CodeObligationSemesterPrecon.Info
066 504 Master programme Embedded Systems Not specified
066 507 Telecommunications Mandatory elective
066 508 Microelectronics and Photonics Mandatory elective

Literature

No lecture notes are available.

Miscellaneous

  • Attendance Required!

Language

German