199.098 Design-for-Trust in VLSI Circuits
Diese Lehrveranstaltung ist in allen zugeordneten Curricula Teil der STEOP.
Diese Lehrveranstaltung ist in mindestens einem zugeordneten Curriculum Teil der STEOP.

2022S, VU, 2.0h, 3.0EC, wird geblockt abgehalten

LVA-Bewertung

Merkmale

  • Semesterwochenstunden: 2.0
  • ECTS: 3.0
  • Typ: VU Vorlesung mit Übung
  • Format der Abhaltung: Präsenz

Lernergebnisse

Nach positiver Absolvierung der Lehrveranstaltung sind Studierende in der Lage...

After successful completion of the course, students are able to...

- Understand integrated circuit design and manufacturing flow and the supply chain
- Understand and apply integrated circuit testing and design-for-testability techniques
- Discuss security and trust vulnerabilities of integrated circuits
- Define red-team blue-team approach in hardware security
- Understand, assess, and compare state-of-the-art design and detection solutions in mitigating the security and trust vulnerabilities

Furthermore, students will have obtained knowledge and comprehension of topics described below. 

Inhalt der Lehrveranstaltung

The lecturer of this course will be Prof. Ozgur Sinanoglu / New York University Abu Dhabi.

Contact details: os22@nyu.edu 

This course covers topics related to security and trustworthiness of electronic hardware. The focus of the course is on the Integrated Circuit (IC) supply chain vulnerabilities and potential remedies in the form of design-for-trust, i.e., proactive techniques employed at the design stage to protect the IC from a variety of supply chain threats. Lectures and in-class discussions on recent research papers cover the following topics: 

Design and manufacturing flow of integrated circuits, testing, and design-for-testability infrastructure (2 hours)  

Integrated circuit supply chain vulnerabilities; hardware Trojans, reverse engineering and Intellectual Property (IP) piracy, counterfeiting, overproduction (2 hours)

Detection techniques for hardware Trojans and counterfeit chips (2 hours) Design-for-Trust techniques: logic locking, split manufacturing, and IC camouflaging (2 hours)

Threat models, attacks, and defenses in logic locking (4 hours) Machine learning in the context of hardware security (2 hours) Scan attacks and mitigation techniques (2 hours)

Fault injection and mitigation techniques (2 hours)

Hardware security in the context of emerging technologies: random number generators, physically unclonable functions (PUFs) (2 hours)  

Methoden

Lectures will be given by the instructor through powerpoint slides which will be provided to the students before each class. A part of some of the lectures may be dedicated to electronic design automation (EDA) tool usage demos for the students. A part of some of the (last 3-4) lectures may include student-group presentations on select topics; technical papers will be provided to the students to study in preparation of these presentations.   

Prüfungsmodus

Prüfungsimmanent

Weitere Informationen

This is a guest professor course of the TU Wien Informatics Doctoral School / Doctoral College "Resilient Embedded Systems".

The course is open to all PhD students and interested Master students.

Course Schedule: May 30 - June 3 & June 20 - 24

May 30-June 3: Everyday, two hours (anytime in the day)
June 20-24: Everyday, two hours (anytime in the day)  

Literature

- Trustworthy Hardware Design: Combinational Logic Locking Techniques, Muhammad Yasin, Prof. Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Springer, 2020, Electronic ISBN: 978-3-030-15334-2

- The Next Era in Hardware Security, Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Shaloo Rakheja, Ozgur Sinanoglu, Springer, 2021, ISBN: 978-3-030-85791-2

- 20-30 technical papers that will be made available to the students at the beginning of the course   

Vortragende Personen

Institut

LVA Termine

TagZeitDatumOrtBeschreibung
15:00 - 17:0030.05.2022 - 03.06.2022Seminarraum DE0110 Design-for-Trust in VLSI Circuits
15:00 - 17:0020.06.2022 - 22.06.2022Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Do.15:00 - 17:0023.06.2022 Treitlstrasse 3, library of second floorDesign-for-Trust in VLSI Circuits
Fr.15:00 - 17:0024.06.2022Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Design-for-Trust in VLSI Circuits - Einzeltermine
TagDatumZeitOrtBeschreibung
Mo.30.05.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Di.31.05.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Mi.01.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Do.02.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Fr.03.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Mo.20.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Di.21.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Mi.22.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
Do.23.06.202215:00 - 17:00 Treitlstrasse 3, library of second floorDesign-for-Trust in VLSI Circuits
Fr.24.06.202215:00 - 17:00Seminarraum DE0110 Design-for-Trust in VLSI Circuits
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Leistungsnachweis

There will be a final exam, which together with students’ performance in their in-class presentations, will be used to assign a final grade.  

LVA-Anmeldung

Von Bis Abmeldung bis
14.02.2022 00:00 29.05.2022 23:59

Anmeldemodalitäten

Please register in TISS.

Curricula

Literatur

Es wird kein Skriptum zur Lehrveranstaltung angeboten.

Vorkenntnisse

Good understanding of digital logic design and algorithms.  

Weitere Informationen

  • Anwesenheitspflicht!

Sprache

Englisch