After successful completion of the course, students are able to...
- derive a verification plan for digital circuits- plan and implement the complete verification process (Requirements, Tracability, Reviews, etc.) - understand and apply established verification methods- test digital circuits according to industrial standards- derive or adapt complext (simulation specific) VHDL modules and libraries- use, extend or develop OSVVM based test environments- apply assertion-based verification methods (PSL, SVA)- understand the basics of UVM- understand the basics of SystemVerilog-based test environments and designs- apply established simulation tools
Since decades digital circuits enrich our lives in various areas. Due to the high complexity of modern circuit applications as well as specific requirements concerning reliability and safety, verification has already become an integral part of chip development projects. This lecture will cover the verification process of digital circuits in detail. Starting from requirements engineering and verification planning, it will continue to the implementation of modern testbenches which are often significantly more complex than the RTL code to be verified.
Simulation based circuit circuit verification is widely used in industry and will hence be covered in detail: Established methodologies as well as respective frameworks will be introduced and practically applied in numerous lab experiments. The course puts a focus on VHDL-based test environments, but SystemVerilog and the powerful and complex UVM will be introduced and accompanied by suitable lab assignments as well.
Students will get deep insights how scalable and re-usable test environments can be designed and how interfaces of the unit-under-test can be abstracted by means of virification units (Bus Functional Models, Driver, Monitors). The aim of every verification campaigne is high test coverage. In the lecture it will be outlined how to obtain that by means of directed and random testing and how to measure it (Requirements Converage, Code Coverage, Functional Coverage, Assertion Coverage).
the course comprises a lecture aprt as well as practical parts like two larger projects and several smaller assignments
******** ECTS Breakdown 75h (3 ECTS) ************
18h Lectures 1h Final Exam40h Verification Project (groups of 2 or 3)16h Small exercises===75h
******** Grading Mode************
- Verification Project: 40%- Small Exercises: 20%- Final Exam (oral): 40%
Assignments:
- Verification Project: 2x (Midterm, final)- Small Exercises: continuously during the semester
