191.127 Industrial Hardware Verification
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2022S, VU, 2.0h, 3.0EC


  • Semester hours: 2.0
  • Credits: 3.0
  • Type: VU Lecture and Exercise
  • LectureTube course
  • Format: Presence

Learning outcomes

After successful completion of the course, students are able to...

- derive a verification plan for digital circuits
- plan and implement the complete verification process (Requirements, Tracability, Reviews, etc.)
- understand and apply established verification methods
- test digital circuits according to industrial standards
- derive or adapt complext (simulation specific) VHDL modules and libraries
- use, extend or develop OSVVM based test environments
- apply assertion-based verification methods (PSL, SVA)
- understand the basics of UVM
- understand the basics of SystemVerilog-based test environments and designs
- apply established simulation tools

Subject of course

Since decades digital circuits enrich our lives in various areas. Due to the high complexity of modern circuit applications as well as specific requirements concerning reliability and safety, verification has already become an integral part of chip development projects. This lecture will cover the verification process of digital circuits in detail. Starting from requirements engineering and verification planning, it will continue to the implementation of modern testbenches which are often significantly more complex than the RTL code to be verified.

Simulation based circuit circuit verification is widely used in industry and will hence be covered in detail: Established methodologies as well as respective frameworks will be introduced and practically applied in numerous lab experiments. The course puts a focus on VHDL-based test environments, but SystemVerilog and the powerful and complex UVM will be introduced and accompanied by suitable lab assignments as well.

Students will get deep insights how scalable and re-usable test environments can be designed and how interfaces of the unit-under-test can be abstracted by means of virification units (Bus Functional Models, Driver, Monitors). The aim of every verification campaigne is high test coverage. In the lecture it will be outlined  how to obtain that by means of directed and random testing and how to measure it  (Requirements Converage, Code Coverage, Functional Coverage, Assertion Coverage).

Teaching methods

the course comprises a lecture aprt as well as practical parts like two larger projects and several smaller assignments

Mode of examination


Additional information

******** ECTS Breakdown 75h (3 ECTS) ************

18h Lectures
1h Final Exam
40h Verification Project (groups of 2 or 3)
16h Small exercises



Course dates

Mon14:00 - 15:0007.03.2022Sem.R. DA grün 02 C - GEO Vorbesprechung
Mon14:00 - 18:0014.03.2022 - 09.05.2022Sem.R. DA grün 02 C - GEO Vorlesung
Mon13:00 - 17:0027.06.2022Sem.R. DA grün 02 C - GEO Final Exam
Industrial Hardware Verification - Single appointments
Mon07.03.202214:00 - 15:00Sem.R. DA grün 02 C - GEO Vorbesprechung
Mon14.03.202214:00 - 18:00Sem.R. DA grün 02 C - GEO Vorlesung
Mon21.03.202214:00 - 18:00Sem.R. DA grün 02 C - GEO Vorlesung
Mon28.03.202214:00 - 18:00Sem.R. DA grün 02 C - GEO Vorlesung
Mon25.04.202214:00 - 18:00Sem.R. DA grün 02 C - GEO Vorlesung
Mon02.05.202214:00 - 18:00Sem.R. DA grün 02 C - GEO Vorlesung
Mon09.05.202214:00 - 18:00Sem.R. DA grün 02 C - GEO Vorlesung
Mon27.06.202213:00 - 17:00Sem.R. DA grün 02 C - GEO Final Exam

Examination modalities

******** Grading Mode************

- Verification Project: 40%
- Small Exercises: 20%
- Final Exam (oral): 40%


- Verification Project: 2x (Midterm, final)
- Small Exercises: continuously during the semester


Course registration

Begin End Deregistration end
01.03.2022 08:00 18.03.2022 23:59


Study CodeObligationSemesterPrecon.Info
066 938 Computer Engineering Mandatory elective


No lecture notes are available.


if required in English