191.110 Hardware Verification
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2018S, VU, 3.0h, 3.0EC, to be held in blocked form


  • Semester hours: 3.0
  • Credits: 3.0
  • Type: VU Lecture and Exercise

Aim of course

The course will start by introducing the Hardware verification domain and the functional verification in the design cycle. The student will learn how to efficiently verify a chip functionality through studying the hardware verification tools and methodologies (Metric Driven Verification Planning, Verification Environment, Metrics Definition and Collection, Monitors and Checkers, Verification Closure, Automated test generation). The course will also introduce the student to industrial standard verification technologies like OVM and UVM. System Verilog language for functional verification will be studied and applied through laboratory sessions.

Subject of course

Course Outlines


-       Hardware verification domain (1 Week)

  • Introduction to formal Hardware verification
  • Functional verification in the design cycle

-       Hardware verification tools and methodologies (2 Weeks)

  • Verification Environment
  • Metric Driven Verification Planning
  • Metrics Definition and Collection
  • Monitors and Checkers
  • Verification Closure
  • Automated test generation

-       System Verilog for functional verification (5 Weeks)

-       Industrial standard verification technologies (4 Weeks)

  • Universal Verification Methodology (UVM)
  • Open Verification Methodology(OVM)
  • Verification Methodology Manual(VMM)
  • Clock Domain Crossing (CDC)
  • Reset Domain Crossing (RDC)

Additional information

Contact Hours

2 hours lecture + 1.5 hour laboratory per week for 12 weeks 

ECTS Breakdown 75h (3 ECTS)

-       24h lectures and examination

-       18h Laboratory sessions

-       33h Design exercises

N.B. The course will be run in English.



Course dates

Fri16:00 - 18:0023.03.2018 - 29.06.2018Sem.R. DB gelb 09 Lecture
Hardware Verification - Single appointments
Fri23.03.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri13.04.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri20.04.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri27.04.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri04.05.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri18.05.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri25.05.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri01.06.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri08.06.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri15.06.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri22.06.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Fri29.06.201816:00 - 18:00Sem.R. DB gelb 09 Lecture
Course is held blocked

Examination modalities


The course grade will be based on 3 practical design projects and two exams.

-       Mid-term Exam: 20 %.

-       Three practical design projects each will be graded with 15%.

-       Final Exam: 35 %.

Course registration

Begin End Deregistration end
22.03.2018 12:00


Study CodeObligationSemesterPrecon.Info
066 938 Computer Engineering Mandatory elective


No lecture notes are available.

Previous knowledge

-       Hardware and circuits design

-       Basic concept of Hardware Description Languages

-       Systems Engineering and design cycle