The course will start by introducing the Hardware verification domain and the functional verification in the design cycle. The student will learn how to efficiently verify a chip functionality through studying the hardware verification tools and methodologies (Metric Driven Verification Planning, Verification Environment, Metrics Definition and Collection, Monitors and Checkers, Verification Closure, Automated test generation). The course will also introduce the student to industrial standard verification technologies like OVM and UVM. System Verilog language for functional verification will be studied and applied through laboratory sessions.

Course Outlines

-       Hardware verification domain (1 Week)

• Introduction to formal Hardware verification
• Functional verification in the design cycle

-       Hardware verification tools and methodologies (2 Weeks)

• Verification Environment
• Metric Driven Verification Planning
• Metrics Definition and Collection
• Monitors and Checkers
• Verification Closure
• Automated test generation

-       System Verilog for functional verification (5 Weeks)

-       Industrial standard verification technologies (4 Weeks)

• Universal Verification Methodology (UVM)
• Open Verification Methodology(OVM)
• Verification Methodology Manual(VMM)
• Clock Domain Crossing (CDC)
• Reset Domain Crossing (RDC)

Contact Hours

2 hours lecture + 1.5 hour laboratory per week for 12 weeks 

ECTS Breakdown 75h (3 ECTS)

-       24h lectures and examination

-       18h Laboratory sessions

-       33h Design exercises

N.B. The course will be run in English.

Grading

The course grade will be based on 3 practical design projects and two exams.

-       Mid-term Exam: 20 %.

-       Three practical design projects each will be graded with 15%.

-       Final Exam: 35 %.

-       Hardware and circuits design

-       Basic concept of Hardware Description Languages

-       Systems Engineering and design cycle