Course Description
The course introduces advanced FPGA design techniques. Emphasis is placed on timing, area, power constraints analysis and optimization. Partial reconfiguration, run time reconfiguration techniques and applications will be studied. Design for synthesis is introduced through different experimental applications. Design verification methodologies will be investigated. Hands on experiments using both design and simulation software tools and FPGA demonstration boards will be designed to explore the introduced topics.
Course Outline s (3 hours per week for 12 weeks + one week for the final exam)
- Speed Optimization (2 Weeks)
- Throughput
- Latency
- Delay paths
- Clock Domains
- Area Optimization (2 Weeks)
- Rolling the pipeline
- Logic reuse
- Sharing Logic resources
- Reset circuits
- Power Optimization (1 Week)
- Clock control and dynamic power consumption
- Clock gating
- Input control for power minimization
- Design for Synthesis (4 Weeks)
- Synthesis optimization
- Tradeoffs
- Floorplanning
- Place and route optimization
- Partial Reconfiguration (2 Weeks)
- Concept and techniques
- Partial reconfiguration for area and power optimization
- Partial reconfiguration for fault tolerance
- Simulation and verification (1 Week)
- Advanced simulation techniques
- Formal verification techniques
An introduction to organization and contents of the course will be given on Wed, Oct 4, at 10:15 in room BA02A (Getreidemarkt)
ECTS breakdown:
20h ... presence in the lectures
40h ... solution of the design problems
15h ... preparation for the exam
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75h ... equals 3 ECTS
