the following competences shall be conveyed:

• deal with challenging (timing) issues in digital design (esp. clock domain crossing)
• understand the theoretical underpinningsof the synchronous design style and its alternatives
• choose the appropriate style for a given problem
• understand the involved limitations

• basic concept and limitations of synchronous design
• metastability: causes and effects, modelling, MTBU estimation and measurement
• design and implementation of synchronizers for different settings
• GALS-Systems (timing domain crossing, pausable clocking)
• internal design, function and limitations of the basic building blocks of asynchronous design: Muller C-Element and Mutual Exclusion Element
• asynchronous design methods (bundled data, delay insensitive), handshake principles (2-phase/4-phase) and timing models (bundled data, delay insensitive,...)
• fundamental description methods for asynchronous design
• comparison of synchronous and asynchronous logic

ECTS breakdown:

27h ...   presence in the lecture / exercise
24h ...   solving the homework assignments
24h ...   preparation for the exam
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75h ...  equals 3 ECTS

The course comprises lectures as well as several blocks during which exercises that have been assigned as homework are discussed. The overall grading considers contributions made during the lectures and the discussion blocks (20%), the quality of the homeworks (40%), and the performance in a final written exam (40%).

The didactic concept comprises a mix of classic lecture for conveying the basics, and exercises for a first application of the material (and partly an extension through self-study). In the accompanying (optional) lab some design problems need to be solved for the application of the knowlede in a practical setting. This will put the graduate in the position to directly and effectively apply the acquired skills in practice.