182.701 HW/SW Codesign
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2018W, LU, 4.5h, 4.5EC


  • Semester hours: 4.5
  • Credits: 4.5
  • Type: LU Laboratory Exercise

Aim of course

Practical implementation of a combined hardware / software system. Optimisation trough partitioning into hardware and software components.

Subject of course

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code that is not optimised enough by the compiler in assembly
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization

Additional information

ECTS Breakdown

99.5 h    Solving the task assignments
      4 h    Preparation of the mid-term presentation
      4 h    Preparation of the final presentation
      5 h    Presence at the presentations/exercise interviews
112.5 h ( = 4.5 ECTS)



Course dates

Tue09:00 - 11:0002.10.2018 Freihaus FH4 (2nd floor, yellow area)Course introduction
Fri10:00 - 12:0005.10.2018 ECS Library (Treitlstraße 3/2nd floor)Nios II/Qsys Introduction and Demonstration
Thu10:00 - 12:0013.12.2018 ECS Library (Treitlstraße 3/2nd floor)Midterm presentations

Examination modalities

At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to get familiar with the development platform provided (Terasic DE2-115) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus, Custom Instructions).

After the introductory task, the project phase begins, where an assignment is solved in groups of three. At the beginning of December mid-term presentations will be held. These presentations should contain a well-thought-out solution concept as well as a status report of the project. (Note that it is not required to have a fully working solution yet). You will be graded based on your concept and presentation. This presentation should also give you the opportunity to get feedback from other groups.

To complete the project an exercise interview in the lab is required. There you will be tested for your knowledge about the implementation details as well as the theoretical background (e.g. algorithms) of the application. In addition, there will be a final presentation and discussion, where all groups present their work.

The introductory task is rewarded with 15 points, where at least 8 points must be achieved in order to successfully complete the course. For the mid-term presentation and the concept another 35 points can be earned. The final solution at the end of the semester is rewarded with a maximum of 50 points (note that group members may be assessed differently).

Solutions with with very good performance may be awarded bonus points.

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.

Course registration

Begin End Deregistration end
17.09.2018 14:00 19.10.2018 23:59 19.10.2018 23:59



No lecture notes are available.



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