182.701 HW/SW Codesign
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2016W, LU, 4.5h, 4.5EC

Properties

  • Semester hours: 4.5
  • Credits: 4.5
  • Type: LU Laboratory Exercise

Aim of course

Practical implementation of a combined hardware / software system. Optimisation trough partitioning into hardware and software components.

Subject of course

Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:

  • Code optimization (C-level)
  • Rewriting code that is not optimised enough by the compiler in assembly
  • Adding application-specific instructions to perform common operations to the instruction set of the processor
  • Transferring functionality into hardware (designing (or finding) appropriate modules and integrating them)

The required knowledge includes in particular:

  • VHDL hardware design
  • C Software development
  • Computer architecture - instruction set, pipelining, memory organisation (SRAM, DRAM, I-/D-cache, scratchpad, register)
  • Understanding of algorithms - loop unrolling, pipelining, parallelization

Additional information

ECTS Breakdown

104.5 h Solving the task assignment
     4 h    Preparation of the final presentation
     4 h    Exercise interview incl. preparation time
-----------------------------------------------
112.5 h ( = 4.5 ECTS)

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Mon10:00 - 12:0003.10.2016Seminarraum Techn. Informatik Lab Introduction

Examination modalities

At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to get to know the development platform provided (Terasic DE2-115) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus). Who successfully solves this task, may enter the group phase, where in groups of three, the actual assignment is worked on. This is handed in followed by an exercise interview where students are tested for knowledge of their implementation details as well as details of the algorithms used in the application.

The individual work is rewarded with maximally 15 points, another 15 points for a solution presentation at the end of the semester, the application along with the exercise interview is rewarded with a maximum of 70 points (i.e., group members may be assessed differently).

The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.

Course registration

Begin End Deregistration end
19.09.2016 14:00 11.10.2016 23:59 21.10.2016 23:59

Curricula

Study CodeObligationSemesterPrecon.Info
066 504 Master programme Embedded Systems Not specified
066 938 Computer Engineering Mandatory1. Semester

Literature

No lecture notes are available.

Miscellaneous

Language

if required in English