Practical implementation of a combined hardware / software system. Optimisation trough partitioning into hardware and software components.
Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Didactic procedure: The task consists of implementing the specified application on the FPGA. Typically, a pure software solution is created first, whose performance is highly unlikely to meet the specified minimum. Subsequently, weaknesses are identified in an appropriate analysis and systematically eliminated. Examples of necessary steps are:
The required knowledge includes in particular:
ECTS Breakdown
104.5 h Solving the task assignment 4 h Preparation of the final presentation 4 h Exercise interview incl. preparation time-----------------------------------------------112.5 h ( = 4.5 ECTS)
At the beginning of the semester a small task needs to be solved in individual work. Its main goal is to get to know the development platform provided (Terasic DE2-115) as well as the used software tools (Altera Quartus, QSYS, NiosII IDE) and the processor (NiosII) with its connectivity options (Avalon bus). Who successfully solves this task, may enter the group phase, where in groups of three, the actual assignment is worked on. This is handed in followed by an exercise interview where students are tested for knowledge of their implementation details as well as details of the algorithms used in the application.The individual work is rewarded with maximally 15 points, another 15 points for a solution presentation at the end of the semester, the application along with the exercise interview is rewarded with a maximum of 70 points (i.e., group members may be assessed differently).The grading is: (S1) to 87.5 pt., (U2) to 75 pt., (B3) to 62.5 pt., (G4) to 50 pt., (N5) below.