After successful completion of the course, students are able to

• name the main differences between hardware and software designs
• use basic VHDL commands and concepts
• demonstrate the behavior of hardware modules described in VHDL
• develop hardware designs with an internal state based on textual specifications
• implement small hardware designs using the hardware description language VHDL
• describe the development process of  a proper implementation strategy
• discuss solutions for problems that appear in real world implementations
• describe the tool design flow and useful mechanisms to control it
• explain the single steps of verification
• conduct testing of an implementation fully automatically

Hardware Development

• motivation and introduction
• key properties and differences to software design
• challenges and hardware description languages

VHDL

• entity, architecture and configuration
• structural and behavioral programming
• testbenches, components and packages
• process, sensitivity list and control flow commands
• state machines, three process method
• data types, attributes, libraries, subprograms, ....

Hardware Modeling

• design flow including verification
• specification, partitioning and design descriptions
• handling real life problems
• state machine design
• programming towards code reusability
• synthesis and optimizations
• functional/formal verification, automated testing

Tools

• Quartus (synthesis)
• Questasim (verification)

• short presentation of tools Quartus and QuestaSim
• explanations on code examples (available for download on TUowncloud)
• online voting system for votings during the lecture
• voluntary training examples in TUWEL
• lecture streaming and recordings using LectureTube (available in TUWEL)

• heavily blocked at begin of semester to assure quick introduction to VHDL (required especially for LU Digital Design and Computer Architecture)
• recordings (slides+audio) will be available in TUWEL after the lecture
• used tools are presented in the lecture

ECTS Breakdown

18 h    Lecture time
19.5 h Continuous engagement with the lecture contents, preparation time for final exam
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37.5h  (= 1.5 ECTS)

written exam on paper, cheat sheet (see TUWEL) will be provided

slides, audio recordings, literature links and examples for training are available in TUWEL

• logic gates (OR, MUX, FF, etc.)
• Mealy / Moore automata
• Y-diagram
• control flow concepts (if-then-else, loops, etc.)
• synchronous circuit design
• hardware design flow including verification