The central aims of the lab are: (1) illustrating the design flow of a digital ASIC (FPGA) at a practical example, first use of the typical tools (2) gaining experience with the handling of a logic analyzer, exploration of its possibilities and limitations (3) gaining first experience with the design and debugging of digital circuits on the example of a processor which is to be imlemented

contents of the lectures "Digital Design", "Hardware Modeling" and "Computer Organzation and Design", in particular design flow (synthesis & simulation) as well as testing & debugging of a VHDL design, practical handling of digital measurement instruments, architecture of a processor

ECTS Breakdown

 75 h      Tasks first part (Digital design basics)
 15 h      Preperation for midterm exam
 75 h      Tasks second part (Computer architecture)
 22.5 h   Preperation for final exam
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187.5 h (= 7.5 ECTS)

In the scope of this lab a set of practical problems have to be solved and the solutions documented in a protocol. Similar problems have to be solved in two practical examinations. The elaboration of the problems in the lab is done partially in groups, but the practical examinations are individual. The final grading is composed of the following: * problem solutions and protocols * practical examinations