The central aims of the lab are: (1) gaining experience with the handling of a logic analyzer, exploration of its possibilities and limitations (2) illustrating the design flow of a digital ASIC (FPGA) at apractical example, first use of the typical tools (3) gaining first experience with debugging of a digital design
In the scope of this lab a set of practical problems has to be solved and the solution documented in a protocol. At the end of the course, a similar problem has to be solved in a practical examination. The elaboration of the problems in the lab is done in groups, but the final examination is individual. The final grading is composed of the following: * multiple-choice test at the beginning of each new lab exercise * protocols * practical test at the end of the lab
