182.045 Digital Design
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2010W, LU, 2.0h, 3.0EC, to be held in blocked form


  • Semester hours: 2.0
  • Credits: 3.0
  • Type: LU Laboratory Exercise

Aim of course

The central aims of the lab are: (1) gaining experience with the handling of a logic analyzer, exploration of its possibilities and limitations (2) illustrating the design flow of a digital ASIC (FPGA) at apractical example, first use of the typical tools (3) gaining first experience with debugging of a digital design

Subject of course

contents of the accompanying lecture, in particular design flow (VHDL & simulation) as well as testing & debugging of a VHDL design practical handling of digital measurement instruments

Additional information

attendance of the kick-off meeting is compulsory (group formation, deadlines, workflow)



Course dates

Tue10:00 - 12:0005.10.2010EI 10 Fritz Paschke HS - BI Vorbesprechung: POLZER
Course is held blocked

Examination modalities

In the scope of this lab a set of practical problems has to be solved and the solution documented in a protocol. At the end of the course, a similar problem has to be solved in a practical examination. The elaboration of the problems in the lab is done in groups, but the final examination is individual. The final grading is composed of the following: * multiple-choice test at the beginning of each new lab exercise * protocols * practical test at the end of the lab

Course registration

Begin End Deregistration end
19.09.2010 00:00 06.10.2010 23:59

Registration modalities

Location: WWW


Study CodeSemesterPrecon.Info
033 533 Medical Informatics
033 535 Computer Engineering 5. Semester


INSTITUT FÜR TECHNISCHE INFORMATIK- Embedded Computing Systems http://ti.tuwien.ac.at

Preceding courses

Continuative courses